In a semiconductor integrated circuit and/or a system including a semiconductor integrated circuit, for example, a clock generated by a clock generation circuit, such as a PLL (Phase Locked Loop) circuit, is supplied to a circuit which performs operations, such as calculation, in synchronization with a rising or falling timing of the clock. In this case, for example, the clock is supplied to a circuit at a position away from the clock generation circuit via a clock path including a plurality of stages of buffer circuits (called clock buffers).
Note that, conventionally, there have been a technique for correcting the duty ratio of a clock generated from a PLL or the like to 50:50, and a technique for varying the duty ratio in accordance with the scale and/or characteristics of a circuit receiving the clock. Note that the duty ratio of 50:50 indicates that in one cycle of clock the percentage occupied by the pulse width at an H (High) level is 50% and the percentage occupied by the pulse width at an L (Low) level is 50%.
Japanese Laid-open Patent Publication No. 2005-159613
Japanese Laid-open Patent Publication No. 2004-348573
Japanese Laid-open Patent Publication No. 2005-294947
However, due to variations in the characteristics of transistors included in a buffer circuit of a clock path, when a clock arrives at a circuit operating with the clock, the duty ratio of the clock differs from an intended one and thus there is a possibility that the circuit does not operate properly.